Flash memory is widely used for peripheral storage in computer systems, and even for primary storage in portable devices. The NAND flash memory was invented by Dr. Fujio Masuoka of Toshiba in 1987. Flash memory uses electrically-erasable programmable read-only memory (EEPROM) cells that store charge on a floating gate. Cells are typically programmed by an avalanche current, and then erased using quantum-mechanical tunneling through a thin oxide. Unfortunately, some electrons may be trapped in the thin oxide during program or erase. These trapped electrons reduce the charge stored in the cell on subsequent program cycles, assuming a constant programming voltage. Often the programming voltage is raised to compensate for trapped electrons.
As the density and size of flash memory has increased, the cell size has been shrunk. The thickness of oxides including the tunneling oxide has also been reduced. The thinner oxides are more susceptible to trapped charges and sometimes fail more easily. The floating gate of NAND flash is used to trap electrons. The number of electrons in the floating gate can affect the voltage level of the output. The different level of voltage is achieved by controlling the number of electrons trapped in the depletion layer during the write process. The ever smaller floating gate area often limits the maximum number of electrons that can be trapped (now just several hundred electrons). Due to program/read interference the electrons can leak or trap into the floating gate. This electron number change will affect the voltage output level change and change the read result.
The number of program-erase cycles that a flash memory is able to withstand (or is spec'ed at) was around 100,000 cycles, which allowed for a lengthy lifetime under normal read-write conditions. However, the smaller flash cells have experienced a disturbingly higher wear and newer flash memories may be spec'ed at less than 10,000 program-erase cycles for two-level cells and about 600 for Triple-Level Cells (TLC). If current trends continue, future flash memories may only allow for 300 program-erase cycles. Such a low endurance could severely limit the applications that flash memory could be used for, and have severe impacts for Solid-State-Disk (SSD) applications.
One method to increase the density of flash memory is to store more than one bit per memory cell. Different voltage levels of the cell are assigned to different multi-bit values, such as four voltage ranges for a two-bit cell. However, the noise margins are reduced for the multi-level-cell (MLC) and TLC flash technologies and endurance problems are exacerbated.
It is expected that the underlying flash technology will have lower and lower endurance in the future. Flash drives may compensate for the lower wear tolerance of the underlying flash memories by a variety of techniques. For example, a DRAM buffer on the flash drive may act as a write-back cache, reducing the number of writes to the underlying flash memories when the host performs writes to the same data location.
What is desired is a flash drive that compensates for lower wear tolerances of underlying flash memory devices. A super-endurance flash drive is desired that uses a barrage of advanced management techniques that together reduce the number of writes to flash, hence reducing program-erase cycles on the underlying flash memory. A super-endurance flash drive constructed from low-endurance flash memory is desired.